1. Field of the Invention
The present invention relates to a semiconductor device 10 and an information processing system including the same, and more particularly to a semiconductor device including a mode register for setting an operation mode and the like and an information processing system including the same.
2. Description of Related Art
Some semiconductor memory devices, typified by a DRAM (Dynamic Random Access Memory), include a mode register for setting their operation mode (see Japanese Patent Application Laid-Open No. 2002-133866). Operation modes to be set in the mode register may include the values of an additive latency (AL), a CAS latency (CL), and a CAS write latency (CWL), and the impedances of output buffers (see Japanese Patent Application Laid-Open Nos. 2008-60641 and 2009-217926).
DDR4 (Double Data Rate 4) DRAMs have recently been proposed as DRAMs even faster than DDR3 (Double Data Rate 3) DRAMs. DDR4 DRAMs support a new function called “PDA”. The FDA function provides a latency for the rewriting of the mode register and makes it possible to set the mode registers of DRAM chips to respective different values.
A circuit for implementing the PDA function and a method for controlling the same need to have a simple circuit configuration and be a simple control method without increasing the circuit area of the semiconductor device.